If for some reason you really wanted to do process Synthetic Aperture Radar (SAR) data on board a spacecraft, using commercial chips, you could do it. But it would be subject to several constraints and compromises.
Supplying kilowatt-ish electrical power would require large, expensive solar panels to keep pointed at the Sun, and a sophisticated cooling system to pull that same kilowatt out of the electronics as heat and then radiate it back into space. This could be a lot easier if you were operating at low duty cycle - if you could accept a lower duty cycle of measurements or only processing a subset of data to the highest spatial resolution.
For non-mission-critical applications like this, you would not need the same level of rad-hardness as you would for spacecraft control. Since the calculation is so parallelizable, checkpointing and redundancy could make space-based computation viable with standard-issue Earthling CPUs.
(tl;dr if you make a mistake image processing, you can go back and do it again, but if you make a mistake and shut down an engine too soon, rebooting and trying again is a lot trickier.)
The mathematical process of analyzing the data is usually parallelizable, which means the problem can be broken into a large number of smaller problems, each solved separately, and then recombined at the end. A simple method to deal with radiation-induced numerical errors might be to simply solve every problem twice in two separate processors and when there are differences, throw them out and do it again. I'm sure there are more sophisticated ways as well.
Checkpointing is a systematic saving of intermediate results. Each time a small problem is solved you save it. Each time enough small ones have accumulated to calculate a larger intermediate result, you do it, and then save that. This way you can recover quickly from any radiation-induced crashes basically pick up where you left off.
note: I know your question is about x86 processors, the following diverges a little bit from those specifically, but it highlights the push to use more and more off-the-shelf computing power in fault-tolerant architecture to partially replace super-reliable rad-hardened but slow and expensive processors.
FPGA's are discussed within SXSE here: 1, 2, 3, in comments here; 4.
STP-H5 and SpaceCubes:
(more about SpaceCubes here and here.)
Part of the recent CRS-10 mission delivery to the ISS is STP-H5:
ISEM – SpaceCube, CHREC Processors
Validation of new processing technology is one of the most critical areas currently faced in the field of space technology given the rapid advancement of space-based instruments that require more and more processing power from highly reliable processor units. The STP-H5 ISEM (ISS SpaceCube Experiment Mini) will provide validation for hybrid-processing technology to advance that technology’s mission readiness level for future application on small satellites with limited volume for computer equipment.
In recent years, a shift has led from ‘radiation hardened systems’ to ‘radiation tolerant technology,’ that is technology which is susceptible to radiation-induced upsets but not radiation-induced destructive failures. Employing such systems can yield to a ten- to hundredfold increase in processing power at the cost of some science data due to occasional radiation related upsets that simply have to be tolerated. (emphasis added)
The v1.0 version has around ten times the processing power of the RAD750 OBC at half the power consumption; v2.0 has twenty times the processing power and requires 75% of RAD’s electrical power.
SpaceCube Mini was designed to similar specifications as v2.0 but in a 1U CubeSat form factor – fitting into a 10 x 10 x 10-centimeter volume. Its core is a multifaceted, hybrid space computer known as CSP, CHREC Space Processor. (emphasis added)
CSP combines fixed and reconfigurable CPU and FPGA processing functions using an algorithm that optimizes the use of the specialized resources of the device. A combination of commercial-off-the-shelf and radiation hardened systems creates a processing system with significant processor power and reliability in challenging space environments. (emphasis added)
above: from here, also described by Spacemicro.
Field Programmable Gate Arrays or FPGAs are finding their way into a wide variety of number crunching and signal processing applications. They can be competitive when the tasks have more diversity that would require very large or complex CPU architecture to provide high speed capacity, and especially if there may be a need to adjust or re-optimize signal processing architecture once the unit is in the field (or in orbit in this case).
A good example of that (use of FPGA for signal processing, not necessarily spaceflight) might be the FPGA implemented GPS radio "freely programmable front end and correlator with a custom firmware" mentioned by @Andreas in this excellent answer. The Piksi uses a Xilinx Zynq-7000 All Programmable SoC (AP SoC):
Zynq-7000 All Programmable SoC Product Advantages
The Zynq®-7000 All Programmable SoC (AP SoC) family integrates the software programmability of an ARM®-based processor with the hardware programmability of an FPGA, enabling key analytics and hardware acceleration while integrating CPU, DSP, ASSP, and mixed signal functionality on a single device. Consisting of single-core Zynq-7000S and dual-core Zynq-7000 devices, the Zynq-7000 family is the best price to performance-per-watt, fully scalable SoC platform for your unique application requirements.
Radiation in LEO is not nearly as bad as it is in higher orbits or deep space, except of course if there is some occasional unusual solar activity. As long as your application can remain in LEO and is not critical during solar events, this should all work.
Again, this is not necessarily competitive with doing the math on the surface, but for certain specific applications it may work.