Apollo-11 AGC core memory has 5 wires per core (rather than 3 or 4) - why? I am referring to this image in Wikipedia: https://en.wikipedia.org/wiki/Apollo_Guidance_Computer#/media/File:Apollo_1024_bit_core_memory_module.jpg Peering closely, I see x and y lines that address individual rows and columns of cores. Then I see 3 more lines: one diagonal line that threads all the cores; one line that runs up and down and appears to thread all the cores; one line that runs back and forth across and appears to thread all the cores. Usually there are just one or two such lines (sense/inhibit combined or separate sense & inhibit lines) that thread all the cores on a plane. Any ideas why?
The document General Design Characteristics of the Apollo Guidance Computer shows 4 wires per "donut".
One core, threaded by four wires stores a bit. Two wires select, one writes, and one senses.
Note: this is for the erasable memory, as shown in the image you linked. If I am interpreting the document correctly, the read-only memory had 3 wires per "donut".
The Wikipedia photo is definitely not an AGC core memory. The AGC's memory (both block I and block II) was very compact, and the plane was folded accordion-style to fit in the rectangular module. The AGC's erasable core memory had 4 wires through each core: horizontal and vertical X/Y select lines, a diagonal sense line, and vertical inhibit line. Each AGC plane was 2048 bites in a 64×32 matrix.
As for the core plane in the Wikipedia, it looks familiar, but I don't know what it is from.
I've studied the AGC memory closely; my writeup (with X-rays) is here if you want details of its construction.