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The Apollo guidance computer had 36 K words of core rope ROM. To address 36864 words, a 15 bit memory address for up to 32768 words is not enough, 16 bits are needed.

This Wikipedia article describes the ROM addressing. The 10 lower bits of the address field of an instruction select the word within a 1024 words.

There is an Fbank register of 4 bit to select the ROM bank and 1 bit Sbank extension to address the last 4 kilowords.

But a bit is missing, 10+4+1 is 15 only and we need 16 bits. Therefore the Fbank register should be 5 bits, not 4.

Am I right about the size of the Fbank register?

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That appears to be the description of the Block 1. The Block 2 is the one with 36 kilowords of memory. It additionally seems to be wrong about the number of bits in the Bank register.

https://www.ibiblio.org/apollo/Block1.html#CPU_Architecture_Registers has the Block 1 details, and states that the high 5 bits of the Bank register are used.

https://www.ibiblio.org/apollo/assembly_language_manual.html#Memory_Map has Block 2 details: the FB register again has 5 bits of bank index, and the SB bit is the 16th bit needed to access the last 4 banks.

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