# How did the Apollo guidance computer handle parity bit errors?

The following answers mention the use of parity bits in the Apollo guidance computer:

• this answer to Bits per core for the different versions of the Apollo guidance computer core rope memory?
• this answer to How did the Apollo computers evaluate transcendental functions like sine, arctangent, log?

1. How did the Apollo guidance computer handle parity bit errors?
2. Were these ever encountered during actual missions?
• Probably not like this: youtube.com/watch?v=G6o881n35GU – Organic Marble May 4 at 23:13
• Ha! you made me literally LOL again. My neighbors think I'm certifiable (not to mention "flawed, and imperfect") because of these. – uhoh May 4 at 23:15

1. How did the Apollo guidance computer handle parity bit errors?

According to Apollo 15 Hardware by Delco Electronics,

Parity Alarm

Occurs if any accessed word in fixed or erasable memory whose address is $$10_8$$ or greater contains an even number of "ones." All locations of $$10_8$$ or greater are stored in fixed or erasable memory with odd parity.

$$10_8$$ is octal 10 or decimal 8.

This condition triggers an automatic hardware restart:

A RESTART (hardware) and subsequent AGC/LGC Warning is generated for the following alarms:

• Oscillator Failure
• Transfer Control (TC) Trap
• Parity Alarm
• Nightwatchman Fail
• Interrupt (RUPT) Lock
• Voltage Fail

The RESTART inhibits access to memory temporarily, freezes the computer, stores in process information and then transfers control to address 4000. This address has the information address for the next instruction after a RESTART that the software programmer has provided.

2. Were these ever encountered during actual missions?

According to the Apollo Program Summary Report, the most severe anomaly in the entire GN&C system was a transient voltage which gave an erroneous indication to the computer that the inertial attitude reference had been lost. It also states that an open gimbal rate feedback circuit caused unexpected oscillation of the redundant engine gimbal actuator assembly. However, of the computer itself, it unambiguously states:

The performance of the computer was flawless.

I would interpret that as no parity errors.

In a total of over 25 hours of space flight, the computer has yet to have a transient failure from which the restart feature could be called on to demonstrate its worth.

(credit to @aCVn) That report was published August 1968, before any of the lunar landings.

• ibiblio.org/apollo/hrst/archive/1033.pdf (section XVI, PDF page 10) says that in 1968, in more than 25 flight hours (section XIX, PDF page 11), "No restart has occured in flight.". That's pretty definite, but of course doesn't cover the lunar landing missions. – a CVn May 6 at 13:30
• The comment above looks pretty definitive. Since comments are temporary and can be deleted at any time, would you consider moving that into your answer? – uhoh May 19 at 11:08

What a fascinatingly obscure question :-) It took some digging, so perhaps someone who's actually seen an AGC might know better:

The parity bit was used to verify that data transferred correctly from memory to the registers. That is, the data in the memory was assumed to be correct, and the error was assumed to take place between the electronics that transfer from the core memory to the registers.

If a parity bit error were detected, then a parity alarm would happen. This actually was displayed on the DSKY and caused a restart of the programs currently running. It was so important that a parity circuit existed in the AGC. It was one of many hardware failure detection systems that protected the AGC during such failures. You can read a lot more about the restart system here here, which describes the parity stuff.

I cannot find any reference to a parity alarm ever occurring, but I haven't looked too hard at the moment. I expect it would be in the mission communications logs if it did.

• Very important. Nowadays you get a nice screen from the OS/BIOS and something along the lines of "parity error - system halted" in correctly implemented hardware (single error correction, double error detection ... ) – David Tonhofer May 5 at 12:50
• Right! obscure question of the month :) – Fattie May 5 at 14:23
• Love the old terminology for what we now know as a watchdog circuit ... the "Night Watchman" :) – madscientist159 May 5 at 14:34
• As someone who has seen (and is restoring) an AGC, I can comment on this. Memory did have parity (15 bits data + 1 bit parity). There was no assumption that the data in memory was correct. – Ken Shirriff May 5 at 16:55
• @DavidTonhofer A modern system will more likely make a system log entry when a correctable RAM ECC error is encountered. (Certainly Linux does it that way.) The assumption here is probably that if you care enough to even know that such an error occured, you care enough to have some kind of log monitoring in place, and since it's correctable, there's no reason to halt or reboot the system. – a CVn May 6 at 12:34