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Wikipedia's article on the IBM System/4 Pi says:

The IBM System/4 Pi is a family of avionics computers used, in various versions, on the F-15 Eagle fighter, E-3 Sentry, AWACS, Harpoon Missile, NASA's Skylab, MOL, and the Space Shuttle, as well as other aircraft. The name of the system refers to the number of steradians (4π) in a sphere. Development began in 1965, deliveries in 1967.

It descends from the approach used in the System/360 mainframe family of computers in that members of the family were intended for use in many varied user applications. Previously custom computers had been designed for each aerospace application, which was extremely costly.

It sounds to me like the idea of providing the System/4 Pi was to provide a bit of standardization, but spaceflight involves an elevated exposure to radiation.

Were there any aspects of the system that were further modified for radiation hardening in spaceflight applications, such as special chips or components or did the standard system already have sufficient hardening?

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    $\begingroup$ At that time in history, computers are not nearly vulnerable to radiation as they are now. So is the application (to reliability issues). $\endgroup$
    – user3528438
    May 10, 2019 at 3:52
  • $\begingroup$ @user3528438 I think that's a really important point, thank you! Consider posting a supplemental answer? $\endgroup$
    – uhoh
    May 10, 2019 at 3:53

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The IBM AP-101S used as the flight computer on the Space Shuttle in the latter part of the program was known to ops personnel as the General Purpose Computer (GPC). Each of the 5 GPCs in the Data Processing System (DPS) had 256k (yes k) of CMOS memory.

This memory was volatile and prone to corruption by radiation (Single Event Upsets, SEUs). Thus there were additional bits of memory for each halfword used for Error Correcting Code (ECC), parity checking, and code overwrite protection. A separate microprocessor performed the error checking.

Only the main memory was protected by ECC, CPU registers were not.

The original shuttle GPC, the AP-101B, had non-volatile memory, but the S model was half the size and had greatly reduced power and cooling loads.

Source: Sadly, personal notes. There is an old Shuttle DPS Overview Training manual available online here but this info likely came from the more detailed HW/SW training manual which I did not find online (but it may be available from Wichita State University or Texas Tech)

The photo below shows an AP-101S GPC from the Shuttle Mission Simulator. Personal photograph taken as the Motion Base crew station was being prepared for museum display.

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    $\begingroup$ Wow thank you for the great and well backgrounded answer. It's great that you have and are such a deep library of information! Do you happen to know what kind of memory the non-volatile memory was? For example, was it SRAM, or FLASH, or magnetic Bubble memory, or something else? $\endgroup$
    – uhoh
    May 9, 2019 at 4:43
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    $\begingroup$ I saw a bunch of GPCs in the Shuttle Avionics Integration Lab for the first time about a week ago. I hadn't realized SAIL is a location on the JSC tour, but it is! One of the only actual-size shuttle cockpits that I've seen (instead of overlarge ones for simulators). $\endgroup$
    – Erin Anne
    May 9, 2019 at 6:06
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    $\begingroup$ @uhoh- according to wikipedia, the AP-101B used magnetic core memory (because it was fully matured technology in the late 1970's). $\endgroup$
    – amI
    May 9, 2019 at 6:54
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    $\begingroup$ Yes, core memory was used in the B model. @ErinAnne, the SMS used real GPCs too. I looked through my pictures but I couldn't find a good one of the SMS GPCs, just the cabinet they lived in. $\endgroup$
    – Organic Marble
    May 9, 2019 at 12:08
  • $\begingroup$ @amI Has magnetic core memory been used beyond the Moon? $\endgroup$
    – uhoh
    May 9, 2019 at 12:11

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