I'm having a hard time finding information on the composition of the AGC's registers. Were they also Magnetic Core Memory or something else?


2 Answers 2


CPU Architecture (Registers) All CPU registers are memory mapped (see the next section). The registers at addresses 00-23 (octal) are central to CPU operations, from the point of view of the instruction set. Registers from addresses 00-07 are flip-flops (well, except for 07) internal to the processor; all other registers are specially handled erasable memory locations. Whenever these flip-flop registers are accessed, their contents get copied to their corresponding erasable memory locations. This link is one-way; erasable memory locations 00-07 can never be read, as all attempts to do so will be redirected to the corresponding flip-flops.

The registers at addresses 24-61 are generically referred to as "counters". While the counter registers can be modified under program control, they are typically only set up by the program and are then subsequently automatically incremented or decremented by events such as electrical pulses. The TIME1-TIME6 registers are even more specialized, in that the "pulses" that increment them are actually provided by an oscillator, so that these counters act as timers. Many of the counters can be used to trigger interrupts upon overflow, so that the CPU can use them to detect various hardware conditions or events without having to continuously poll the hardware.

Only the registers 0 to 7 were hardware registers build from flip-flops using NOR gates. Registers 10 to 60 (octal numbers) were memory mapped build with magnetic cores.

To save a lot of logic gates as many as possible registers were located in core memory.

For details see the memory map.

  • $\begingroup$ Thank you very much! $\endgroup$ Dec 1, 2021 at 20:45

A wealth of information on the AGC can be found by poking around here.

To answer your question directly, from General Design Characteristics of the Apollo Guidance Computer available on that page, we have (emphasis added)

The AGC uses three types of memory circuits; one is for a permanent storage of instructions and constants and holds about 24,000 words. The second type is for the temporary storage of intermediate results, modified instructions, and input data. It holds about a 1024 words. Both of these types of memory are relatively economical and dense in terms of the number of words per unit volume. But they also require a comparatively long time to read from and write into (about 12 µsec). The third type of memory, consisting of 16 registers, has a read-write time of about 2 µsec and is about a 1000 times larger in volume than the other two types of memory. This group contains input and output registers which communicate between the computer and the rest of the Apollo system. The central registers participate in the instructions and cause the desired mathematical transformations to be effected. ... The central registers and the input-output registers are made using semiconductor networks (micrologic NOR gates).

  • $\begingroup$ The IO registers were memory mapped using core memory. $\endgroup$
    – Uwe
    Dec 1, 2021 at 17:45
  • $\begingroup$ Memory mapping just means that it's accessible via a memory address. It says nothing about the hardware that is actually used to store and retrieve the value. Page 19 of this link from the page linked above: klabs.org/history/history_docs/mit_docs/1717.pdf explicitly says the input registers were flip-flop based. Your answer above also points out that though the memory mapping resulted in the data being copied to the core memory, that was effectively write-only memory, and only the flip-flops were used for those addresses. $\endgroup$
    – Tristan
    Dec 1, 2021 at 20:50
  • $\begingroup$ There was read read only core memory used for program and constants and also read/write core memory for variable data. $\endgroup$
    – Uwe
    Dec 1, 2021 at 21:28
  • $\begingroup$ Much of the incoming information consists of trains of pulses which must be counted, and the running total must be available to the program. Incrementing of the counters was done with logic, the counter states were stored in the core memory. So these kind of input went thru the core memory. $\endgroup$
    – Uwe
    Dec 1, 2021 at 21:43

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.