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I read this article about "dream mode" in the Curiosity rover. In the article they mention:
... implemented on about 1.2 million logic gates ...
How large would the avionics hardware need to be in order to house 1.2 million logic gates? Are there any pictures which highlight what the hardware looks like relative to the rest of the rover?
I am not an expert in electronics or FPGAs, but a couple of these would fit the bill, I think:
http://www.xilinx.com/products/silicon-devices/fpga/kintex-7q.html
These aerospace grade fpga-chips fit 480,000 in a tiny IC package. I don't think the physical size is much of an issue here, even if we consider that the rover was designed a few years ago, when density wasn't quite as high. The packaging of this particular chip is a 23 mm square; 2.5 mm high.
It's a rather old question, but let me clarify a bit: Rikki-Tikki-Tavi got confused by logic gates versus logic cells - A typical logic cell of a typical FPGA is much more complex than a single logic gate. Some rather rough conversion factor is about 100. Hence, these FPGA are much much more powerfull than needed for this rather purpose.
A FPGA that most likely could do the job (despite the space rating and temperature range) can today be bought for few (single digit) Dollars measuring 4x4 mm^2 - and that's just limited by the amount of inputs and outputs and not by the size of the silicon itself. Sure, radiation hardness, temperature rating and the ten year old hardware used on the rover pays its toll with respect to size (not mentioning the price rising by many orders of magnitude), but you'll get the point.
